1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
A CMOS solid-state imaging device is an example of a solid-state imaging device. In the CMOS solid-state imaging device, two pixels are formed of photodiodes and transistors, which are so-called MOS transistors, and a plurality of pixels are arranged in a predetermined pattern. The photodiodes are photoelectric conversion elements which generate and accumulate signal charges corresponding to the amounts of received light. The MOS transistors transfer the signal charges obtained by the photodiodes.
FIG. 1 is a schematic sectional view illustrating the main part of a CMOS solid-state imaging device 216 according to a related art disclosed in Japanese Unexamined Patent Application Publication No. 11-122532. The solid-state imaging device 216 is applied to an image sensor. FIG. 1 shows the sectional structure of a pixel section of the solid-state imaging device 216.
The solid-state imaging device 216 shown in FIG. 1 includes a p-type substrate 201 made of silicon and pixel separating areas 208 provided in a front surface of the p-type substrate 201. A pixel 200 including a photodiode PD and a plurality of MOS transistors is provided in each of sections separated from each other by the pixel separating areas 208. The MOS transistors include a charge-readout transistor Tr1, a reset transistor Tr2, an amplifier transistor Tr3, and a vertical selection transistor (not shown). The pixel area including the four MOS transistors and the photodiode PD serves as a unit pixel. A plurality of unit pixels are arranged in a two-dimensional matrix.
The photodiode PD includes an n+ type impurity area 203 and an n-type impurity area 202 arranged in order from the surface of the p-type substrate 201 in the depth direction, and also includes a high-impurity-concentration p-type impurity area 204 provided in a surface of the n+ type impurity area 203.
In addition, the charge-readout transistor Tr1 includes a planar-type gate electrode 209 and a source-drain area 205. The planar-type gate electrode 209 is formed above the substrate 201 with a gate insulating film 217 interposed therebetween at a position adjacent to the area where the photodiode PD is formed. The source-drain area 205 is formed of an n+ type impurity area provided in the surface of the substrate 201. The source-drain area 205 serves as a floating diffusion area.
The amplifier transistor Tr3 includes a source-drain area 206, a planar-type gate electrode 211, and a source-drain area 207. The planar-type gate electrode 211 is formed above the substrate 201 with the gate insulating film 217 interposed therebetween at a position adjacent to the area where the source-drain area 206 is formed. The source-drain area 207 is formed of an n+ type impurity area provided in the surface of the substrate 201.
The reset transistor Tr2 includes the source-drain area 205, a planar-type gate electrode 210, and the source-drain area 206. The planar-type gate electrode 210 is formed above the substrate 201 with the gate insulating film 217 interposed therebetween at a position adjacent to the area where the source-drain area 205 is formed. The source-drain area 206 is formed of an n+ type impurity area provided in the surface of the substrate 201.
The source-drain area 206 is connected by a contact portion 212 to a power source line 213 formed above the substrate 201 with an interlayer insulation film 215 interposed therebetween.
Desired wirings 214 are provided in the interlayer insulation film 215.
Thus, each unit pixel 200 includes the photodiode PD and the MOS transistors on the surface of the substrate 201 in the solid-state imaging device 216 according to the related art.
Recently, the pixel size has been reduced to integrate larger number of pixels in the solid-state imaging device. In the solid-state imaging device 216 according to the related art shown in FIG. 1, the photodiode PD and the MOS transistors are arranged along the same plane in the substrate 201 for each unit pixel 200. Therefore, the area of the surface of the substrate 201 corresponding to each unit pixel 200 is desired to be large enough to place the above-mentioned elements. Accordingly, the area of a single pixel is relatively large. In this structure, if the pixel size is reduced, the area of the photodiode PD will also be reduced. As a result, the saturation charge amount (Qs) and sensitivity will also be reduced.
To avoid such a problem, methods of reducing the pixel size by causing a plurality of pixels which are adjacent to each other to use common MOS transistors have been proposed.
For example, methods have been proposed in which a plurality of pixels which are adjacent to each other are caused to use common pixel transistors so that the pixel size can be reduced without reducing the area of the photodiode PD. For example, in a general CMOS solid-state imaging device, a single set of pixel transistors are used in common by four pixels.
In addition, as a completely different approach to prevent the reductions in the saturation charge amount (Qs) and sensitivity due to the reduction in the pixel size, Japanese Unexamined Patent Application Publication No. 2002-513145 proposes a solid-state imaging device including an embedded gate electrode. FIG. 4 shows a CMOS solid-state imaging device 231 including a vertical charge-readout transistor provided with an embedded gate electrode.
The CMOS solid-state imaging device 231 is a back-illuminated solid-state imaging device in which light is incident on a back surface of the substrate. FIG. 4 shows the main part of a pixel section. The CMOS solid-state imaging device 231 includes pixel transistors, which form pixels, on a front surface of a semiconductor substrate 232. In this example, the pixel transistors include a charge-readout transistor Tr1, a reset transistor Tr2, and an amplifier transistor Tr3. A photodiode PD is formed below these pixel transistors in each pixel. The photodiode PD includes an n-type semiconductor area 233 and a high-impurity-concentration p-type semiconductor area (p+ area) 241 formed in the substrate 232 on the front side of the n-type semiconductor area 233. The n-type semiconductor area 233 includes a high-impurity-concentration area (n+ area) 233A which serves as a charge storage area and a low-impurity-concentration area (n area) 233B.
The charge-readout transistor Tr1 is a vertical transistor including a columnar readout gate electrode 236 formed such that the readout gate electrode 236 is disposed in a trench 234 with a gate insulating film 235 interposed between the readout gate electrode 236 and an inner surface of the trench 234. The trench 234 extends in the depth direction from the front surface of the substrate 232 to the n-type high-impurity-concentration area (n+ area) 233A in the photodiode PD. An n-type source-drain area 237, which serves as a floating diffusion (FD) area, is formed in the surface of the substrate 232 such that the n-type source-drain area 237 is in contact with the gate insulating film 235. The vertical gate electrode 236 of the vertical charge-readout transistor Tr1 is formed at a position corresponding to the center of a unit pixel 251, that is, at the center of the photodiode PD. The high-impurity-concentration p-type semiconductor area (p+ area) 241 surrounds a portion of the gate insulating film 235 that is formed in the high-impurity-concentration area (n+ area) 233A of the photodiode PD.
The reset transistor Tr2 includes a pair of n-type source-drain areas 237 and 238 provided in the front surface of the substrate 232 and a planar reset gate electrode 243 formed above the front surface of the substrate 232 with a gate insulating film interposed therebetween. The amplifier transistor Tr3 includes a pair of n-type source-drain areas 238 and 239 provided in the front surface of the substrate 232 and a planar-type gate electrode 240 formed above the front surface of the substrate 232 with the gate insulating film interposed therebetween. Multiple wiring layers in which a plurality of layers of wiring 246 are formed are provided above the substrate 232, on which the pixel transistors Tr1, Tr2, and Tr3 are formed, with interlayer insulation films 245 interposed therebetween. Although not shown in FIG. 4, a color filter is provided on the back surface of the substrate 232, and on-chip microlenses are provided on the color filter at positions corresponding to the pixels. In FIG. 4, reference numeral 250 denotes pixel separating areas.
Although not shown in FIG. 4, signal processing circuits including CMOS transistors are formed in a peripheral circuit section. The CMOS transistors include planar-type gate electrodes.
In addition, as another completely different approach to prevent the reductions in the saturation charge amount (Qs) and sensitivity due to the reduction in the pixel size, Japanese Unexamined Patent Application Publication No. 2005-223084 proposes a solid-state imaging device including an embedded gate electrode.
A CMOS solid-state imaging device is an example of a solid-state imaging device. In the CMOS solid-state imaging device, two pixels are formed of photodiodes and transistors, which are so-called MOS transistors, and a plurality of pixels are arranged in a predetermined pattern. The photodiodes are photoelectric conversion elements which generate and accumulate signal charges corresponding to the amounts of received light. The MOS transistors transfer the signal charges obtained by the photodiodes.
In addition, as a completely different approach to prevent the reductions in the saturation charge amount (Qs) and sensitivity due to the reduction in the pixel size, Japanese Unexamined Patent Application Publication No. 2007-36202 proposes a method of separating light into components in a single pixel by arranging a plurality of photodiodes in a depth direction of a substrate.
Referring to FIG. 2, for example, Japanese Unexamined Patent Application Publication No. 2002-513145 describes a color separation method in which a three-layer structure including an n-type semiconductor layer 102, a p-type semiconductor layer 104, and an n-type semiconductor layer 106 is formed in a p-type Si substrate 100. Blue light, green light, and red light are subjected to photoelectric conversion in the respective layers in order of depth from the surface. In this method, blue, green, and red signals are transmitted to the outside through terminals connected to the respective layers on the surface of the Si substrate 100. This structure utilizes the relationship between the wavelength and the light absorption characteristics in the depth direction. Thus, the color separation can be achieved by a single pixel, and generation of false colors can be suppressed. Therefore, low-pass filters can be omitted. In addition, since no color filter is used, red, green, and blue light components having different wavelengths are incident on a unit pixel. Therefore, loss in the amount of light can be reduced. However, the photodiode which performs photoelectric conversion of the red light component having a long wavelength and accumulates the generated signal charge is formed at a depth of about 2 μm from the surface of the silicon substrate 100. Therefore, the distance between the photodiode and the corresponding output terminal on the substrate surface is large, and it is difficult to completely transfer the signal charge accumulated by the photodiode.
To solve such a problem, Japanese Unexamined Patent Application Publication No. 2007-36202 describes a structure in which potential barriers are disposed between the photodiodes arranged in the depth direction. In the case where the potential barriers are disposed between the photodiodes, a signal charge accumulated in a photodiode disposed at a deep position in the substrate can be easily transferred to a corresponding floating diffusion area. However, when the charge is accumulated in an area distant from the surface of the substrate in the depth direction, it is difficult to apply a sufficient potential variation to the accumulated charge using an electric field applied by a gate electrode formed at the surface of the substrate. Therefore, there is a risk that an afterimage will be generated.
FIG. 3 shows an equivalent circuit of the above-described unit pixel 200. The photodiode PD is connected to a source of the charge-readout transistor Tr1, and a drain of the charge-readout transistor Tr1 is connected to a source of the reset transistor Tr2. A drain of the reset transistor Tr2 is connected to a drain of the amplifier transistor Tr3. A source of the amplifier transistor Tr3 is connected to a drain of a vertical selection transistor Tr4. In addition, the floating diffusion (FD), which corresponds to a connection point between the charge-readout transistor Tr1 and the reset transistor Tr2, is connected to a gate of the amplifier transistor Tr3. A source of the vertical selection transistor Tr4 is connected to a vertical signal line 221.
A vertical reading pulse φTG is applied to a gate of the charge-readout transistor Tr1. A reset pulse φR is applied to a gate of the reset transistor Tr2. A vertical selection pulse φSEL is applied to a gate of the vertical selection transistor Tr4.